The present application relates generally to semiconductor devices, and more specifically to vertical field effect transistors (VFETs) and their methods of production.
Conventional vertical FETs are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical pillar defines the channel with the source and drain located at opposing ends of the pillar. An advantage of the vertical FET is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control.
Modern transistors are manufactured using gate-first or gate-last (also known as replacement metal gate) process flows, which may include hybrid approaches such as a gate-first method for NMOS and a gate-last method for the more difficult PMOS transistor. With the proliferation of high-k dielectrics (e.g., dielectric materials having a dielectric constant greater than silicon nitride), it has been suggested that the high-temperature steps that follow high-k and metal gate depositions cause an adverse shift in threshold voltage, affecting PMOS performance in particular.
In view of the foregoing, it would be advantageous to provide a manufacturing process for a vertical field effect transistor that is compatible with a gate-last approach.